The invention relates generally to the design of semiconductor integrated circuits (ICs). More specifically, the invention relates to a method for designing and adapting port shapes in such a way as to optimize resources during detailed routing.
An integrated circuit (IC) is a device which includes a plurality of electronic components, e.g. transistors, resistors, diodes etc.). These components are interconnected to form multiple circuit components (gates, cells, memory units etc.) on the IC. Interconnects between the components are formed by stripes of metal wiring arranged in planar layers (so-called “metal layers” M1, M2, M3, . . . ) within the IC. Up to ten (or even more) of these metal layers may be stacked on top of each other.
During IC design, a circuit description of the IC—characterizing the IC's properties—is transformed into a geometric description (so-called layout) by using geometric shapes that represent different materials and devices on the IC. For example, wire segments interconnecting the IC's components are commonly represented by rectangular lines, whereas the IC components themselves are commonly represented as geometric objects of varying shapes and sizes. The circuit modules (corresponding to the geometric representations of the IC's circuit components) are typically illustrated with ports on their sides or within the component; these ports are used to interconnect the IC component to power supply and other IC components within the design. A net is typically defined as a collection of ports that need to be electrically connected. The list of all or some of the nets in the layout is referred to as a netlist. Thus, the netlist specifies a group of nets, which, in turn, specify the required interconnections between a set of ports.
As part of IC design, in a so-called placement step, circuit modules are placed on the various metal layers, thus determining the alignment, orientation and position of the circuit modules on the chip. Subsequently, a routing step is carried out in which the circuit modules are interconnected. Routing is generally carried out in three phases. Global routing generates a “coarse” route for the interconnect lines that are to connect the ports of the net. After global routes have been created, local routing creates specific individual routing paths for each net. Based on these routing paths, final port accesses are created in a detailed routing step.
U.S. Pat. No. 7,032,201 B1 discloses a detailed routing method for a region of an IC layout which contains a plurality of routable elements such as port areas which are to be connected by a net. The method makes use of a decomposition in terms of a plurality of nodes located in the region; some of the nodes are located at a boundary of the routable elements. Based on these nodes, the region is triangulated, and the triangles thus defined are used for generating routes in the region under consideration. By iteratively dividing the region into smaller and smaller triangles, a fine-grained route can be determined. Triangulation may also be performed on the port geometries.
While the decomposition described in U.S. Pat. No. 7,032,201 B1 can be used as a basis for detailed routing, this provides only a topological route, i.e. a general plan for how to route a net in the region under consideration. Method of U.S. Pat. No. 7,032,201 B1 generally does not provide a specific geometric path to implement this topological route and therefore does not furnish means of extracting or influencing the geometrical properties (shape, size etc.) of the routable elements.
When geometrical properties (boundary, size etc.) of ports are defined during detailed routing, the ports are typically assigned shapes in such a way that routing access is possible under all circumstances. As a consequence, the areas of these ports are generally defined larger than actually needed. The excess area assigned to these ports constricts the free space resources available for wiring of other ports. Since routing resources are limited, this impedes detailed routing and may cause wiring congestion.